1. Field of the Invention
The present invention is related to a device for increasing chip testing efficiency and method thereof, and particularly to a device and method thereof that utilize an address compression method to increase chip testing efficiency.
2. Description of the Prior Art
Please refer to FIG. 1A, FIG. 1B, and FIG. 1C. FIG. 1A, FIG. 1B, and FIG. 1C are diagrams illustrating a test for a memory chip according to the prior art. As shown in FIG. 1A, a logic voltage “D0” is written to banks BK0, BK2 and a logic voltage “D1” is written to banks BK1, BK3 simultaneously. Then, logic voltages stored in the banks BK0, BK2 and logic voltages stored in the banks BK1, BK3 are read simultaneously, and the logic voltages stored in the banks BK0, BK2 are compared with the logic voltage “D0”, and the logic voltages stored in the banks BK1, BK3 are compared with the logic voltage “D1” to determine whether the memory chip is passed. Similarly, as shown in FIG. 1B, the logic voltage “D0” is written to the banks BK0, BK3 and the logic voltage “D1” is written to the banks BK1, BK2 simultaneously. Then, logic voltages stored in the banks BK0, BK3 and logic voltages stored in the banks BK1, BK2 are read simultaneously, and the logic voltages stored in the banks BK0, BK3 are compared with the logic voltage “D0”, and the logic voltages stored in the banks BK1, BK2 are compared with the logic voltage “D1” to determine whether the memory chip is passed. In addition, as shown in FIG. 1C, the logic voltage “D0” is written to the banks BK0, BK1, BK2, and BK3 simultaneously. Then, logic voltages stored in the banks BK0, BK1, BK2, and BK3 are read simultaneously, and the logic voltages stored in the banks BK0, BK1, BK2, and BK3 are compared with the logic voltage “D0” to determine whether the memory chip is passed.
Though the prior arts in FIG. 1A, FIG. 1B, and FIG. 1C can reduce time for testing the memory chip, only two test patterns can be inputted in FIG. 1A and FIG. 1B and only one test pattern can be inputted in FIG. 1C. Therefore, the prior arts in FIG. 1A, FIG. 1B, and FIG. 1C have lower diversity, resulting in insufficient test coverage.